FIG. 1 shows a typical CMOS transistor configuration, in accordance with the prior art. In the example of FIG. 1, a preferred direction for an interconnect level (metal-1) is parallel to that for gate electrode (gate) wires, as seen for metal-1 wire 105 and gate wire 103. Gate wire 103 overlaps a diffusion shape 101, forming a transistor with a source or drain (S/D) node that is connected to metal-1 wire 105 by a contact 106. Wire 105 requires a non-rectangular shape, i.e., a shape with a bend, to allow it to overlap a contact 102 which connects to a gate wire 107. FIG. 1 also shows a gate electrode wire 104 that requires a bend to overlap a gate contact 108, which connects to a metal-1 wire 109.
The typical CMOS transistor configuration of FIG. 1 illustrates a number of features that may increase manufacturing difficulty. For example, contacts for S/D and gate connections are not aligned, gate and metal wire widths are variable, spacing between wire shapes is variable, wire center lines are variably spaced apart, and a ratio of filled to non-filled space for gate and metal-1 levels is variable. These features may cause parametric and defect yield loss in advanced semiconductor processes due to associated lithographic effects, CMP (chemical mechanical planarization) dishing, and/or other manufacturing imperfections. Therefore, it is of interest to define a semiconductor device layout methodology that accounts for layout characteristics which adversely affect manufacturability.